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Newbie Question: Using Includes in Verilog

  1. Newbie Question: Using Includes in Verilog

    This is a very basic question. I would appreciate your help. I have a
    Xilinx FPGA Verilog project that containts several files. I would like
    to use an include file for some definitions that I would like to use
    in several files.

    I addeded the line:

    `include "definitions.v"

    to one of the .v modules containing the FPGA code.

    definitions.h contains the following:


    //definitions.h

    parameter NO_SELECT = 16'h00,
    REG1_ADDRESS = 16'h01,
    REG2_ADDRESS = 16'h02,
    REG3_ADDRESS = 16'h03,
    REG4_ADDRESS = 16'h04,
    REG5_ADDRESS = 16'h05,
    BLOCK1_ADDRESS = 16'h06,

    REG1_SELECT = 16'h01,
    REG2_SELECT = 16'h02,
    REG3_SELECT = 16'h04,
    REG4_SELECT = 16'h08,
    REG5_SELECT = 16'h10,
    BLOCK1_SELECT = 16'h20;


    From Xilinx ISE I get the following error:

    ERROR:HDLCompilers:26 - "rtl/definitions.v" line 2 expecting 'EOF',
    found 'parameter'

    When I compile in ModelSim I get the following error:
    ** Error: D:/rtl/rf_board_top.v(23): Cannot open `include file
    "definitions.v".

    What am i doing wrong?
    How to get ModelSim to find the include file (it is in the same
    directory as the Verilog modules)?

    Thanks for your help.


  2. Re: Newbie Question: Using Includes in Verilog

    For ISE, the parameter only applies within a module so the include statement
    would be after the port list.
    If you want "global parameters" you need to figure another method; this is
    not how Verilog works.

    For Modelsim, the tool needs to have an appropriate path specified to the
    file. I don't know the option to add the path but I'd try -y as a stab if I
    didn't want to check for "path" in the help.


    wrote in message
    news:cpaj63h4r5oe2kiotf3oknjau3a5g6iu5o@4ax.com...
    > This is a very basic question. I would appreciate your help. I have a
    > Xilinx FPGA Verilog project that containts several files. I would like
    > to use an include file for some definitions that I would like to use
    > in several files.
    >
    > I addeded the line:
    >
    > `include "definitions.v"
    >
    > to one of the .v modules containing the FPGA code.
    >
    > definitions.h contains the following:
    >
    >
    > //definitions.h
    >
    > parameter NO_SELECT = 16'h00,
    > REG1_ADDRESS = 16'h01,
    > REG2_ADDRESS = 16'h02,
    > REG3_ADDRESS = 16'h03,
    > REG4_ADDRESS = 16'h04,
    > REG5_ADDRESS = 16'h05,
    > BLOCK1_ADDRESS = 16'h06,
    >
    > REG1_SELECT = 16'h01,
    > REG2_SELECT = 16'h02,
    > REG3_SELECT = 16'h04,
    > REG4_SELECT = 16'h08,
    > REG5_SELECT = 16'h10,
    > BLOCK1_SELECT = 16'h20;
    >
    >
    > From Xilinx ISE I get the following error:
    >
    > ERROR:HDLCompilers:26 - "rtl/definitions.v" line 2 expecting 'EOF',
    > found 'parameter'
    >
    > When I compile in ModelSim I get the following error:
    > ** Error: D:/rtl/rf_board_top.v(23): Cannot open `include file
    > "definitions.v".
    >
    > What am i doing wrong?
    > How to get ModelSim to find the include file (it is in the same
    > directory as the Verilog modules)?
    >
    > Thanks for your help.
    >




  3. Re: Newbie Question: Using Includes in Verilog

    On Fri, 08 Jun 2007 19:24:28 GMT, freeagent.20.oracle@xoxy.net wrote:


    >//definitions.h
    >
    >parameter NO_SELECT = 16'h00,
    > REG1_ADDRESS = 16'h01,
    > REG2_ADDRESS = 16'h02,
    > REG3_ADDRESS = 16'h03,
    > REG4_ADDRESS = 16'h04,
    > REG5_ADDRESS = 16'h05,
    > BLOCK1_ADDRESS = 16'h06,
    >
    > REG1_SELECT = 16'h01,
    > REG2_SELECT = 16'h02,
    > REG3_SELECT = 16'h04,
    > REG4_SELECT = 16'h08,
    > REG5_SELECT = 16'h10,
    > BLOCK1_SELECT = 16'h20;
    >
    >



    I believe that the syntax of your definitions.h file is wrong.

    `define NO_SELECT 16'h00
    `define REG1_ADDRESS 16'h01

    (and so on) should work, to judge from my experience with a comparable
    situation.

    Hope that helps.
    --
    Per ardua ad nauseam

  4. Re: Newbie Question: Using Includes in Verilog

    On Fri, 08 Jun 2007 19:24:28 GMT, freeagent.20.oracle@xoxy.net wrote:

    Thanks for the help. That enabled me to get it working.

    I moved the `include after the port definitions and that fixed ISE
    problem.

    I changed the properties on each .V source file to include the
    directory where the include file was located (even though it was the
    same directory as the source .v files). This fixed the ModelSim
    problem.

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