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Xiinx ERROR:PhysDesignRules:10

  1. Xiinx ERROR:PhysDesignRules:10

    Hi all,

    I've got a design that can be built in 2 different configurations,
    controlled via a VHDL constant / if-generate in a sub-module. Each
    configuration uses a particular set of I/O pins and leaves the others
    dangling. The Xilinx tools won't let me generate a bit file for this design.

    ERROR:PhysDesignRules:10 - The network is completely
    unrouted.

    I've tried tri-stating the unused I/O pins (pin <= 'Z') but the problem
    persists. I can't drive 0 or 1 because they're effectively open-collector.

    Is there any way I can circumvent this error? Turn if off? Or fool it?

    BTW it's perhaps complicated by the fact that I inherited this design -
    the top level is a massive schematic and it is built using Altium's DXP.

    Regards,

    --
    Mark McDougall, Engineer
    Virtual Logic Pty Ltd,
    21-25 King St, Rockdale, 2216
    Ph: +612-9599-3255 Fax: +612-9599-3266

  2. Re: Xiinx ERROR:PhysDesignRules:10

    I am not sure if Xilinx's KEEP attribute might help or not.. Please
    check the Xilinx's constraints Guide, may be that might help you.

    ####################################################
    Eg: in UCF --
    NET "xyz" KEEP;
    ####################################################

    -- parag

    On Oct 10, 11:18 pm, Mark McDougall wrote:
    > Hi all,
    >
    > I've got a design that can be built in 2 different configurations,
    > controlled via a VHDL constant / if-generate in a sub-module. Each
    > configuration uses a particular set of I/O pins and leaves the others
    > dangling. The Xilinx tools won't let me generate a bit file for this design.
    >
    > ERROR:PhysDesignRules:10 - The network is completely
    > unrouted.
    >
    > I've tried tri-stating the unused I/O pins (pin <= 'Z') but the problem
    > persists. I can't drive 0 or 1 because they're effectively open-collector.
    >
    > Is there any way I can circumvent this error? Turn if off? Or fool it?
    >
    > BTW it's perhaps complicated by the fact that I inherited this design -
    > the top level is a massive schematic and it is built using Altium's DXP.
    >
    > Regards,
    >
    > --
    > Mark McDougall, Engineer
    > Virtual Logic Pty Ltd,
    > 21-25 King St, Rockdale, 2216
    > Ph: +612-9599-3255 Fax: +612-9599-3266




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