
Random Number Generation in VHDL
Hello members,
I would like to know if VHDL already has functions defined to generate
Random Numbers.
If not, which would be the best algorithm for generating random
numbers for implementation on an FPGA.
Thank you

Re: Random Number Generation in VHDL
Good luck with the random numbers, but if you want pseudorandom:
http://en.wikipedia.org/wiki/LFSR.
Xilinx also has an excellent document on LFSRs with polynomials up to
about 1000 bits or so.

Re: Random Number Generation in VHDL
> I would like to know if VHDL already has functions defined to generate
> Random Numbers.
google is your friend :)
http://www.velocityreviews.com/forum...generator.html
> If not, which would be the best algorithm for generating random
> numbers for implementation on an FPGA.
The answer to this question will depend on the FPGA architecture that
you're using, as well as your needs for cryptographic security. This
is because, when it comes to pseudorandom number generation, "best"
can be subjective. e.g., "best" speed? "best" area? "best" power
consumption? "best" random numbers (cryptographically secure)?
This is a wellstudied area; I recommend that you do some reading to
see what suits you ...
http://en.wikipedia.org/wiki/Random_number_generator
Kris

Re: Random Number Generation in VHDL
On 24 Jan., 18:54, FPGA wrote:
> Hello members,
>
> I would like to know if VHDL already has functions defined to generate
> Random Numbers.
>
> If not, which would be the best algorithm for generating random
> numbers for implementation on an FPGA.
>
> Thank you
Hello FPGA,
Maybe it's offtopic for you, because you want to implement in FPGA
rather than simulating your design,
but have you seen this package :
http://www.janick.bergeron.com/wtb/packages/random1.vhd ?
Ed

Re: Random Number Generation in VHDL
FPGA wrote:
> I would like to know if VHDL already has functions defined to generate
> Random Numbers.
> If not, which would be the best algorithm for generating random
> numbers for implementation on an FPGA.
LFSR are pretty popular for random numbers, and very easy to
implement in an FPGA.
 glen

Re: Random Number Generation in VHDL
On Jan 25, 1:01*am, glen herrmannsfeldt wrote:
> FPGA wrote:
> > I would like to know if VHDL already has functions defined to generate
> > Random Numbers.
> > If not, which would be the best algorithm for generating random
> > numbers for implementation on an FPGA.
>
> LFSR are pretty popular for random numbers, and very easy to
> implement in an FPGA.
>
>  glen
I just found out that I need random number generator just for
simulation. I do not need to synthesize it. Some feedback on this
would be helpful. I am having a look at some of the links posted here.
Thanks

Re: Random Number Generation in VHDL
On Fri, 25 Jan 2008 06:44:10 0800 (PST),
Ann wrote:
>I just found out that I need random number generator just for
>simulation. I do not need to synthesize it. Some feedback on this
>would be helpful. I am having a look at some of the links posted here.
OK, that's easy. The math_real package contains an excellent
random number generator that you can adapt for your own purposes.
use ieee.math_real.all;
...
process
variable R: real;
variable S1, S2: positive := 42;
 seed variables, change initialization to
 get a different random number stream
begin
...
uniform(S1, S2, R);
...
This modifies seed variables S1 and S2 ready for the
next call to uniform()  DON'T DO ANYTHING ELSE with
these two variables. And it also puts a random number
into R, uniformly distributed in the real range 0.0 to
0.99999...; you can then very easily scale this
number to get whatever you want. A couple of examples:
 Get the integer value "5" with 20% probability,
 and "7" with 80% probability
if R < 0.2 then
x := 5;
else
x := 7;
end if;

 Get an integer in the range LO to HI (where LO, HI
 are both integers and LO<=HI)
R := R * real(HILO) + real(LO);
x := integer(floor(R));
HTH

Jonathan Bromley, Consultant
DOULOS  Developing Design Knowhow
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Re: Random Number Generation in VHDL
On Fri, 25 Jan 2008 15:13:14 +0000,
Jonathan Bromley wrote:
>OK, that's easy.
Not so easy, it seems: apologies for this
offbyone error...
>  Get an integer in the range LO to HI (where LO, HI
>  are both integers and LO<=HI)
> R := R * real(HILO) + real(LO);
That should be
R := R * real(HI+1LO) + real(LO);
Sorry

Jonathan Bromley, Consultant
DOULOS  Developing Design Knowhow
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Re: Random Number Generation in VHDL
I usually use a maximal LFSR to obtain psuedo random numbers.
The following link will give you some good information.
http://www.xilinx.com/ipcenter/catal.../docs/lfsr.pdf
I like Appendix B wich lists the tap points up to 168bits for a maximal
length LFSR.
The following would generate psudeo random 64 bit numbers starting with seed
value 1.
entity generator is
port (
clk:in bit;
aut bit_vector(63 downto 0));
end;
achitecture processflow of generator is
begin
CLKEDrocess
variable temp:bit_vector(63 downto 0) :=
X"0000_0000_0000_0001";
begin
temp := temp(63 downto 0 ) & (temp(63) xor temp(62) );
a <= temp;
wait until (clk = '0');
end process
end
"glen herrmannsfeldt" wrote in message
news:k4qdnWK4LOGX5wTanZ2dnUVZ_sHinZ2d@comcast.com...
> FPGA wrote:
>
>> I would like to know if VHDL already has functions defined to generate
>> Random Numbers.
>
>> If not, which would be the best algorithm for generating random
>> numbers for implementation on an FPGA.
>
> LFSR are pretty popular for random numbers, and very easy to
> implement in an FPGA.
>
>  glen
>

Re: Random Number Generation in VHDL
On Fri, 25 Jan 2008 10:40:11 0800,
Dwayne Dilbeck wrote:
>I usually use a maximal LFSR to obtain psuedo random numbers.
>
>The following link will give you some good information.
>http://www.xilinx.com/ipcenter/catal.../docs/lfsr.pdf
>
>I like Appendix B wich lists the tap points up to 168bits for a maximal
>length LFSR.
>
>The following would generate psudeo random 64 bit numbers starting with seed
>value 1.
>
>entity generator is
> port (
> clk:in bit;
> aut bit_vector(63 downto 0));
>end;
>
>
>achitecture processflow of generator is
>begin
> CLKEDrocess
> variable temp:bit_vector(63 downto 0) :=
>X"0000_0000_0000_0001";
> begin
> temp := temp(63 downto 0 ) & (temp(63) xor temp(62) );
> a <= temp;
> wait until (clk = '0');
> end process
>end
aaargh.... note that this gives you one pseudorandom BIT per
clock cycle.... but the 64bit words are painfully strongly
correlated from one cycle to the next. You need to clock
your Nbit LFSR for at least N cycles before pulling the
next Nbit value from it.
Even then, the random numbers aren't brilliantly random
(or at least that's what I am led to understand  I don't
have a particularly good grip on the somewhat scary math)
but LFSRs are indeed a good source of quasirandom stuff
for noncritical applications. Just remember to clock
them enough times!

Jonathan Bromley, Consultant
DOULOS  Developing Design Knowhow
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.