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HDL - simulation vs synthesis

  1. HDL - simulation vs synthesis

    I run Xilinx ISE v10.1 and use VHDL. I have put together a fairly
    small circuit that merely sends out solid colors and sync signals on a
    VGA line. During the active video portion of time, a color should
    show up on the screen. The color depends on which of three switches
    on my development board are turned on. There is one for red, green
    and blue.

    Now the behavioral simulation tells me that the code works exactly as
    it is supposed to, however, when I actually implement it on my
    development board it does not work. I have heard of this type of
    problem many times, but have no idea where to begin in finding the
    fault.

    Just so nobody thinks I'm trying too much at once, I did try it
    without the switches and told it to just output a solid, unchanging,
    color. That worked. I tested it for each of the three colors.

    The RTL schematic that is generated by ISE shows me that both the
    three switches and the red_out, green_out, and blue_out do not exist,
    but none of the warning messages that show up tell me that they were
    removed. Can somebody tell me where to begin in solving this issue?
    Perhaps a list of things to try / look for or link me to some possible
    solution or list of solutions.

  2. Re: HDL - simulation vs synthesis

    Try a gate-level simulation and see what is going on.

    Are you sure there are no warning messages?

    Cheers,
    Jon

  3. Re: HDL - simulation vs synthesis

    jared.pierce@gmail.com wrote:

    > The RTL schematic that is generated by ISE shows me that both the
    > three switches and the red_out, green_out, and blue_out do not exist,

    There's your problem.
    No registers are being inferred.
    Are you using a synchronous process?

    -- Mike Treseler

  4. Re: HDL - simulation vs synthesis

    Thanks for the help guys. I made several changes and the problem
    finally went away. It works! I still don't know why it wasn't
    working so I plan to back up what I have and insert one test problem
    at a time to see what happens(of the problems I fixed). I still don't
    get why the RTL schematic would bother to include a DFF where the Q
    wasn't connected to anything. It would have been just as good not to
    include it. Any hints on that one?

  5. Re: HDL - simulation vs synthesis

    Hi Jared,
    synthesis tools like ISE XST try to optimize the design as best as possible.
    If you leave the output of a flipflop open, it's of no use for the
    design anymore and the Flipflop is deleted. Then the gates to the former
    flipflops input have open outputs and are deleted as well. That goes on
    and on until the Input from your switch is reached.
    This behavior may cause no warnings but infos so read them as well.
    Anyway, if you have an idea about what elements your design should have
    and the synthesis result is suspiciously small you should check the
    reports for deleted flipflops and combinatorical circuits.

    Similar thing happens when inputs have a fixed connection to high or
    low. The synthesis tool calculates the optimised logic and the result
    may be fixed outputs, so the design will be reduced to some fixed
    connections to high and low at the output.

    Sometimes whole designs vanish this way. :-)

    Have a nice synthesis
    Eilert


    jared.pierce@gmail.com schrieb:
    > Thanks for the help guys. I made several changes and the problem
    > finally went away. It works! I still don't know why it wasn't
    > working so I plan to back up what I have and insert one test problem
    > at a time to see what happens(of the problems I fixed). I still don't
    > get why the RTL schematic would bother to include a DFF where the Q
    > wasn't connected to anything. It would have been just as good not to
    > include it. Any hints on that one?
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