Using the FF @ Port pin

On Wed, 12 Nov 2008 19:55:14 +0100
Jan wrote:

> Dear All,
>
> I can see in the documentation on the Sparton 3A that it has a FF
> placed near the output pin. I would like to use this to ensure that
> the output from a BUS is 100% in sync so routing don't affect the
> timing.
>
> Is there a ATTRIBUTE to give the signal or how do I tell the router
> to use this last FF?
>
> I'm using ISE 10.1
>
> Thank you in advance!
>
> Regards
> Jan

You're looking for the IOB attribute. That said, in my experience, the
tools do a pretty aggressive job of moving things that can be pushed
into the IOB flops into them just on the default AUTO setting.

--
Rob Gaddi, Highland Technology
Email address is currently out of order

On Nov 12, 2:17*pm, Rob Gaddi wrote:
> On Wed, 12 Nov 2008 19:55:14 +0100
>
>
>
> Jan wrote:
> > Dear All,
>
> > I can see in the documentation on the Sparton 3A that it has a FF
> > placed near the output pin. I would like to use this to ensure that
> > the output from a BUS is 100% in sync so routing don't affect the
> > timing.
>
> > Is there a ATTRIBUTE to give the signal or how do I tell the router
> > to use this last FF?
>
> > I'm using ISE 10.1
>
> > Thank you in advance!
>
> > Regards
> > * *Jan
>
> You're looking for the IOB attribute. *That said, in my experience, the
> tools do a pretty aggressive job of moving things that can be pushed
> into the IOB flops into them just on the default AUTO setting.
>
> --
> Rob Gaddi, Highland Technology
> Email address is currently out of order

That may be true, but if you assign "IOB = TRUE" you will get a
warning if
this doesn't happen for the flip-flop in question. A bit easier than
scanning
a large output bus in the FPGA editor.

On Nov 13, 7:55*am, Jan wrote:
> I can see in the documentation on the Sparton 3A that it has a FF placed
> * near the output pin. I would like to use this to ensure that the
> output from a BUS is 100% in sync so routing don't affect the timing.

Hi Jan,
In theory, you shouldn't need to force the tools to do it. You should
have an "offset out" timing constraint (along with period constaints
on clks) so then its up to the tools to do what is necessary to meet
that timing. I.e. let the tools decide if they need to use the IOB or
not. If you don't use an offset out constraint and manually force the
flop into the IOB with an attribute, you can get caught out if the
tools decide to silently ignore your attribute some time in the
future. On the other hand, if the tools fail to meet a timing
constaint the problem is obvious (I regard the timing report as a must
check item before releasing a binary FPGA image.)

(If its a large bus, one advantage of not having all bits change at
the same time is less simultaneously switching output(SSO) noise. The
FPGA datasheet has SSO guidelines...)

Cheers
Andrew

Andrew FPGA wrote:
> On Nov 13, 7:55 am, Jan wrote:
>> I can see in the documentation on the Sparton 3A that it has a FF placed
>> near the output pin. I would like to use this to ensure that the
>> output from a BUS is 100% in sync so routing don't affect the timing.
>
> Hi Jan,
> In theory, you shouldn't need to force the tools to do it. You should
> have an "offset out" timing constraint (along with period constaints
> on clks)>


> (If its a large bus, one advantage of not having all bits change at
> the same time is less simultaneously switching output(SSO) noise. The
> FPGA datasheet has SSO guidelines...)

Thank you. That is very good advices! Why didn't I think of the that?
:-) I'll try the offset constraint.

My bus is quite large, so I think I'll try to look into the SSO.

Regards
Jan

Jan wrote:
> Dear All,
>
> I can see in the documentation on the Sparton 3A that it has a FF placed
> near the output pin. I would like to use this to ensure that the output
> from a BUS is 100% in sync so routing don't affect the timing.
>
> Is there a ATTRIBUTE to give the signal or how do I tell the router to
> use this last FF?
>
> I'm using ISE 10.1
>
> Thank you in advance!
>
> Regards
> Jan

For any design where you need to insure that an IOB register (in or out)
is used, check the Map Report File (.mrp extension). This is a text
file, and section 6 (in ISE 9.2.03) is a table listing the properties of
all of the IOBs in the design. Included in the table is a column name
Reg(s).

Also, there is pad file, which is another text file with the name,
_pad.txt, that has a comprehensive list of all (used and
unused) of the IOB properties.

If you suddenly start having odd timing problems, check these files and
insure that your IOB registers are still in place.

HTH