How to stop using a signed subtractor

[Database Administrator]

Whilst trying to find out why my borrow out from a subtractor is
behaving incorrectly I noticed that some of my subtractors are signed
subtractors. This was shown by the ISE RTL schematic view. There are no
signed types in the verilog. So how could I have managed to do this?

{COm, Rd_contents}=Rn_contents - shifter_operand - BI;

The synthesis report records the subtractors as 33 bits wide.
shifter_operand, Rn_contents and Rd_contents are all 32 bits wide.

So is there a template for a subtractor using borrow in and borrow out
in verilog? e.g. I coded it wrongly.

Can I change one the data types into unsigned to force XST to make it
into an unsigned subtractor?

Synthesis is verilog 2001. I can use verilog 95 if it would help.

All suggestions gratefully listened to.

I am still learning verilog so please be gentle. Thanks in advance Andy.

[Database Administrator]

On Nov 13, 4:32*pm, Andy Botterill wrote:
> Whilst trying to find out why my borrow out from a subtractor is
> behaving incorrectly I noticed that some of my subtractors are signed
> subtractors. This was shown by the ISE RTL schematic view. There are no
> signed types in the verilog. So how could I have managed to do this?
>
> {COm, Rd_contents}=Rn_contents - shifter_operand - BI;
>
> The synthesis report records the subtractors as 33 bits wide.
> shifter_operand, Rn_contents and Rd_contents are all 32 bits wide.
>
> So is there a template for a subtractor using borrow in and borrow out
> in verilog? e.g. I coded it wrongly.
>
> Can I change one the data types into unsigned to force XST to make it
> into an unsigned subtractor?
>
> Synthesis is verilog 2001. I can use verilog 95 if it would help.
>
> All suggestions gratefully listened to.
>
> I am still learning verilog so please be gentle. Thanks in advance Andy.

Just to understand this better, you're saying that the carry (or
borrow)
out is being messed up in the implementation? i.e. it looks like your
inputs are being sign-extended before the subtraction?

Another thing that bothers me is the lack of parentheses in the
equation.
Subtraction is one of those operators where a- (b - c) is not the
same as (a - b) - c, and if you guess the operator order incorrectly
you can have errors in the output as well.

Verilog 2001 does in fact have signed data types. How did you
define your 32-bit numbers? reg [31:0] foo? integer foo?

You can always force the correct behavior by zero-extending the
inputs yourself as in ({1'b0,a} - {1'b0,b}) - BI

You may want to post this on comp.lang.verilog to get the guru's
view.

Regards,
Gabor

[Database Administrator]

Andy Botterill wrote:


> Can I change one the data types into unsigned to force XST to make it
> into an unsigned subtractor?

> All suggestions gratefully listened to.


http://groups.google.com/group/comp....width-extended

[Database Administrator]

Gabor wrote:
> On Nov 13, 4:32 pm, Andy Botterill wrote:
>> Whilst trying to find out why my borrow out from a subtractor is
>> behaving incorrectly I noticed that some of my subtractors are signed
>> subtractors. This was shown by the ISE RTL schematic view. There are no
>> signed types in the verilog. So how could I have managed to do this?
>>
>> {COm, Rd_contents}=Rn_contents - shifter_operand - BI;
>>
>> The synthesis report records the subtractors as 33 bits wide.
>> shifter_operand, Rn_contents and Rd_contents are all 32 bits wide.
>>
>> So is there a template for a subtractor using borrow in and borrow out
>> in verilog? e.g. I coded it wrongly.
>>
>> Can I change one the data types into unsigned to force XST to make it
>> into an unsigned subtractor?
>>
>> Synthesis is verilog 2001. I can use verilog 95 if it would help.
>>
>> All suggestions gratefully listened to.
>>
>> I am still learning verilog so please be gentle. Thanks in advance Andy.
>
> Just to understand this better, you're saying that the carry (or
> borrow)
> out is being messed up in the implementation? i.e. it looks like your
> inputs are being sign-extended before the subtraction?

I'm not sure where the problem is yet. In my testbench I use this opcode
18 times. 2 times the borrow out (that would be a more obvious name than
COm sorry) is wrong. The borrow out is in the wrong state compared to my
pencil and paper calculations. The result (Rd_contents) is correct based
on the input data.
>
> Another thing that bothers me is the lack of parentheses in the
> equation.
> Subtraction is one of those operators where a- (b - c) is not the
> same as (a - b) - c, and if you guess the operator order incorrectly
> you can have errors in the output as well.
The output side is correct it's the borrow out side that I can't understand.
>
> Verilog 2001 does in fact have signed data types. How did you
> define your 32-bit numbers? reg [31:0] foo? integer foo?
reg [31:0] Rn_contents;
reg [31:0] Rd_contents;
reg [31:0] shifter_operand;
reg CO, COm, CI;
(* KEEP="TRUE" *) wire BI;
I only put the keep in there so that I can monitor the signal.

>
> You can always force the correct behavior by zero-extending the
> inputs yourself as in ({1'b0,a} - {1'b0,b}) - BI

Rn_contents and shifter_operand_out are already the correct size. Do you
really mean sign extend BI?
>
> You may want to post this on comp.lang.verilog to get the guru's
> view.
Let me do some checking before that. Thanks for the help.
>
> Regards,
> Gabor

[Database Administrator]

On Nov 14, 12:40*am, Andy Botterill
wrote:
> Gabor wrote:
> > On Nov 13, 4:32 pm, Andy Botterill wrote:
> >> Whilst trying to find out why my borrow out from a subtractor is
> >> behaving incorrectly I noticed that some of my subtractors are signed
> >> subtractors. This was shown by the ISE RTL schematic view. There are no
> >> signed types in the verilog. So how could I have managed to do this?
>
> >> {COm, Rd_contents}=Rn_contents - shifter_operand - BI;
>
> >> The synthesis report records the subtractors as 33 bits wide.
> >> shifter_operand, Rn_contents and Rd_contents are all 32 bits wide.
>
> >> So is there a template for a subtractor using borrow in and borrow out
> >> in verilog? e.g. I coded it wrongly.
>
> >> Can I change one the data types into unsigned to force XST to make it
> >> into an unsigned subtractor?
>
> >> Synthesis is verilog 2001. I can use verilog 95 if it would help.
>
> >> All suggestions gratefully listened to.
>
> >> I am still learning verilog so please be gentle. Thanks in advance Andy.
>
> > Just to understand this better, you're saying that the carry (or
> > borrow)
> > out is being messed up in the implementation? *i.e. it looks like your
> > inputs are being sign-extended before the subtraction?
>
> I'm not sure where the problem is yet. In my testbench I use this opcode
> 18 times. 2 times the borrow out (that would be a more obvious name than
> COm sorry) is wrong. The borrow out is in the wrong state compared to my
> pencil and paper calculations. The result (Rd_contents) is correct based
> on the input data.
>
> > Another thing that bothers me is the lack of parentheses in the
> > equation.
> > Subtraction is one of those operators where a- (b - c) is not the
> > same as (a - b) - c, and if you guess the operator order incorrectly
> > you can have errors in the output as well.
>
> The output side is correct it's the borrow out side that I can't understand.
>
> > Verilog 2001 does in fact have signed data types. *How did you
> > define your 32-bit numbers? *reg [31:0] foo? *integer foo?
>
> * * reg [31:0] Rn_contents;
> * * reg [31:0] Rd_contents;
> * * reg [31:0] shifter_operand;
> * * reg CO, COm, CI;
> * * (* KEEP="TRUE" *) wire BI;
> * *I only put the keep in there so that I can monitor the signal.
>
>
>
> > You can always force the correct behavior by zero-extending the
> > inputs yourself as in ({1'b0,a} - {1'b0,b}) - BI
>
> Rn_contents and shifter_operand_out are already the correct size. Do you
> really mean sign extend BI?

All of the arguments need to be extended to 33 bits for a proper
result.
The two registers I extended manually needed one more bit. You said
the result was correct which seems to imply that BI is handled
properly,
since a signed BI would actually add instead of subtract one.

>
> > You may want to post this on comp.lang.verilog to get the guru's
> > view.
>
> Let me do some checking before that. Thanks for the help.
>
>
>
> > Regards,
> > Gabor

[Database Administrator]

Gabor wrote:
> On Nov 14, 12:40 am, Andy Botterill
> wrote:
>> Gabor wrote:

I checked my arithmetic again. I got my subtraction wrong for the carry
bit. The result part was good. Please accept my humble apologies.

>>> You can always force the correct behavior by zero-extending the
>>> inputs yourself as in ({1'b0,a} - {1'b0,b}) - BI

My original verilog is good. If I move to another synthesis tool am I
likely to need to sign extend the arguments or not? I want to get into
good habits. Andy

>> Rn_contents and shifter_operand_out are already the correct size. Do you
>> really mean sign extend BI?
>
> All of the arguments need to be extended to 33 bits for a proper
> result.
> The two registers I extended manually needed one more bit. You said
> the result was correct which seems to imply that BI is handled
> properly,
> since a signed BI would actually add instead of subtract one.
>


>>> Regards,
>>> Gabor