Number of GCLKs: 9 out of 8 112% (OVERMAPPED)

[Database Administrator]

I have this problem. Use ISE 9.2 SP4. This problem is solved in ISE
10.1 SP1, but I whant solve this problem in 9.2. Help!!!!

[Database Administrator]

On Nov 14, 2:14*am, axalay wrote:
> *I have this problem. Use ISE 9.2 SP4. This problem is solved in ISE
> 10.1 SP1, but I whant solve this problem in 9.2. Help!!!!

I'd suggest getting rid of at least one clock.

KJ

[Database Administrator]

On Nov 14, 5:54 am, KJ wrote:
> On Nov 14, 2:14 am, axalay wrote:
>
> > I have this problem. Use ISE 9.2 SP4. This problem is solved in ISE
> > 10.1 SP1, but I whant solve this problem in 9.2. Help!!!!
>
> I'd suggest getting rid of at least one clock.
>
> KJ

Or use ISE 10.1. Or both, or all 3!

Build using 10.1. Notice which clocks are assigned to GCLKs. Find
out which of the 9 clocks (from ISE 9.2) are NOT assigned to GCLKs.

Manually assign the 8 favorite clocks to GCLKs.

Disable the option to 'automatically promote to GCLK' or whatever it's
called. It moves around from version to version.

It looks like Xilinx finally addressed the issue where more nets would
be promoted to GCLKs than there were GCLKs available. Previously,
GCLK_max was set according to the family, and was not adjusted for the
particular chip used. I had fun with this one when I did a XC2V4000 -
> XC2V3000 migration.

Where's Peter when we really need him?


PS: KJ has a very valid point. 9 clocks is a LOT of clocks, you can
probably cut this number in half by using gated clocks where
appropriate.

[Database Administrator]

LittleAlex wrote:
> On Nov 14, 5:54 am, KJ wrote:
>> On Nov 14, 2:14 am, axalay wrote:
>>
>>> I have this problem. Use ISE 9.2 SP4. This problem is solved in ISE
>>> 10.1 SP1, but I whant solve this problem in 9.2. Help!!!!
>> I'd suggest getting rid of at least one clock.
>>
>> KJ
>
> Or use ISE 10.1. Or both, or all 3!
>
> Build using 10.1. Notice which clocks are assigned to GCLKs. Find
> out which of the 9 clocks (from ISE 9.2) are NOT assigned to GCLKs.
>
> Manually assign the 8 favorite clocks to GCLKs.
>
> Disable the option to 'automatically promote to GCLK' or whatever it's
> called. It moves around from version to version.
>
> It looks like Xilinx finally addressed the issue where more nets would
> be promoted to GCLKs than there were GCLKs available. Previously,
> GCLK_max was set according to the family, and was not adjusted for the
> particular chip used. I had fun with this one when I did a XC2V4000 -
>> XC2V3000 migration.
>
> Where's Peter when we really need him?
>
>
> PS: KJ has a very valid point. 9 clocks is a LOT of clocks, you can
> probably cut this number in half by using gated clocks where
> appropriate.

Probably just a matter of semantics, but gated clocks shoud be avoided
like the plague for synchronous designs. Presumably you meant using
clock enables where appropriate.

[Database Administrator]

On Nov 14, 2:53 pm, Paul Urbanus wrote:
>
> Probably just a matter of semantics, but gated clocks should be avoided
> like the plague for synchronous designs. Presumably you meant using
> clock enables where appropriate.

You are correct.